Design of Reconfigurable FFT Processor With Reduced Area And Power

Fast fourier transform (FFT) is an efficient implementation of the discrete fourier transform (DFT). The main objective of the project is to implement a reconfigurable FFT processor with reduced power and area in order to provide system designers and engineers with the flexibility to meet different system requirements. This paper proposes a low power and area efficient FFT architecture using Single Delay Feedback (SDF). The proposed methodology is based on Radix factorization which is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. An FFT processor design methodology with optimal power-area trade-off using feasible parallel architectures and radix factorizations is obtained.